- SoC Solution
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RTL Design, Platform Design & Verification, FPGA Verification 부터
Design Service 분야의 DFT Insertion, Layout, PKG / Test까지
시스템반도체 개발 및 제작에 필요한 모든 솔루션을 제공합니다.
Design Service Flow
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STEP 1
Spec. Decision
RTL Coding -
STEP 2
Synthesis
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STEP 3
Netlist
Hand-off -
STEP 4
DFT
Service -
STEP 5
Placement
Routing -
STEP 6
Verification
& PG -
STEP 7
Test Vector
Generation -
STEP 8
Failure
Analysis
Design Service Level
Level |
SERVICE 1
Spec. Decision |
SERVICE 2
Synthesis |
SERVICE 3
Netlist |
SERVICE 4
DFT |
SERVICE 5
Placement |
SERVICE 6
Verification |
SERVICE 7
Test Vector |
SERVICE 8
Failure |
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Level 0
Spec. Sign-off Model |
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Level 1
RTL Sign-off Model |
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Level 2
Netlist Sign-off Model |
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Level 3
Layout Sign-off Model |
Total Solution
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FULL CHIP DESIGN
( SPEC / DESIGN )Design / Verification Platform
System Architecture Analysis
Power Management Control
Real Emulation with FPGA
IP Supplier Partnership
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PHYSICAL
( SYNTHESIS / DFT )
IMPLEMENTATIONDFT (SCAN / BIST / JTAG)
STA (Static Timing Analysis)
Synthesis & Timing Closure
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PHYSICAL DESIGN
( AUTO P&R )Hierarchical Physical Design
Low Power Design
Flip Chip Physical Design
Power & Signal Integrity
Physical Verification
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PKG & TEST Develop
( Assembly & TEST )Package Design
Test vector generation
ATE test set-up
Qualification & Reliability
Q.A & Failure analysis
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Mass Production
( SCM )Wafer Business
Full Turn-key Business
(Wafer + PKG + TEST)
Advanced Technology
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- Mobile & Communication
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Mobile AP, 5G Modem,
V2X communication network
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- IoT
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Smart Home, Audio processor, Wi-Fi, RF SoC,
Printer SoC, Wearable
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- Automotive
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ADAS, Cluster, Cockpit, In / Outside Camera,
Dash-board Camera(DVR)
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- Display
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Touch, Timing Controller, RGB / IR Sensor ISP,
Video Scaler, UHD TV SoC
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- AI
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Server AI, NPU, AR Controller,
Micro AI
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- Security
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Digital Security SoC, ISP for CCTV camera,
Block Chain, Set-top box
개발 일정 단축을 효과적으로 지원하는 SoC 설계 솔루션을 제공합니다.
Vision & Mission
Customized
SoC Design Solution
Provider
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01
SoC Design Solution
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Spec-to-Design
SoC System Design
SoC Verification
SoC FPGA protype
Reliable Design Process
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01
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02
SoC Design Platform
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SoC System Platform
SoC Verification Platform
SoC FPGA Platform
ARM Partnership
IP Supplier Partnership
Early Start, Fast Optimize
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02
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03
High-Performance Design
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NoC / Memory System Optimization
Maximize Clock Frequency
Hardening for Computing Clusters
Physical Design Consideration
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03
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04
Low-Power Design
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Power Domain Scenario
Design for Dynamic clock-gating
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04
SoC Design Solution
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01
SoC DesignSystem Architecture
Processing Core
NoC/Memory System
External High-speed Interface
Micro Architecture
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02
SoC VerificationBus Functional Modeling
Module/System Level in a Unified Testbench
UVM methodology with VIP
Bus Traffic Modeling & Performance Verification
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03
SoC FPGA prototypeFPGA Board Design
Connected multiple FPGA targeting
Verification with Firmware
SoC Design Platform
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SoC System Platform
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ARM-based SoC System : Ready for Entry-to-Cutting Edge
3rd Party IP with Partnership
Early Start and Fast Optimization
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SoC Verification Platform
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Systematic Configured & Re-usable Environment
All Verification Cases from Top to Sub in One Environment
Configurable Alternative Models for Integrated Units
Light and Reliable against Integration Issue
Easy Porting your System into One Verification Env.
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SoC FPGA Platform
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FPGA board with SoC System Platform
Fast Emulation for your IP on SoC System Platform
Fast Emulation for your System
Fast Iteration for your IP/System Architecture
Physical
Implementation
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Hardening for
Computing Clusters -
CPU
GPU
NPU
Hash Core
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Physical & Power-aware
Logic Synthesis -
Logic Synthesis with physical information and power scenario
Placement-Aware Multi-Bit Register Banking
Physically aware Clock Gating restructuring
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Design For Testability
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Support advanced DFT solutions Low pin count test with serializer Power Aware DFT Test Fail Diagnosis
Logic / Memory BIST (Built in Self Test) In-System test method against progressive faults in logic area Fault injection simulation for safety analysis of design Shared Bus BIST/BIRA/BISR
SCAN (Advanced DFT Skill) Scan test for improved test coverage for lower DPPM Stuck-At, Bridge, Transition, Path-delay, OCCT, Burn-in
IDDQ Test IDDQ test for additional fault coverage
Boundary Scan Inter-chip connection test method for system level testing
Physical DFT consider Physical Reordering and Repartitioning
Physical Design
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Accurate and
robust timing analysis -
LVF based variability library
Moment-based LVF to cope with non-Gaussian effect
Parametric OCV method
CCS/CCSN-based STA
Statistical Rvia STA
NP-Skewed corner STA for hold timing, min-pulse, and DCD check only
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Physical optimization
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BEOL-aware delay optimization (BEOL resistance increase impacting path delay)
Mixed DDB/MDB Flow
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Physical-aware Timing ECO
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Minimize physical side-effect for ECO
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MIM-aware Timing ECO
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Produce a single ECO file for Multiply Instantiated Module
Accelerate multi-core CPU/GPU timing closure
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01
Dynamic Power OptimizationMulti-supply Voltage & Voltage Island
In-Rush Current prevented power gating
Clock/Memory-Gating
Dynamic Voltage Frequency Scaling
Vector-Driven Optimization
Decap pre-placement method
Merge or split ICG / Multi-bit flip-flop
Low Power CTS (Concurrent Clock and
Data Optimization) -
02
Leakage Power OptimizationMulti-Vth Optimization
Gate-Length Biasing
Sign-off Leakage Optimization
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03
Low Power VerificationLow power static rule check
Power-aware Simulation
Power-aware equivalence check
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01
Power Integrity SolutionPower Plan based on Early Prototyping Analysis
Dynamic Voltage Drop Analysis
Static Power Analysis
Power EM / BUMP Current
P/G Resistance check
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02
Signal Integrity SolutionSignal EM
Glitch Noise analysis
Clock Jitter validation
Duty-cycle distortion methodology
Clock Propagation Check
3-row decap inverter on CTS